1. Field of the Invention
The present invention generally relates to high density semiconductor devices. More particularly, the present invention relates to a method and apparatus for nucleating deposition of high quality, high-K dielectrics, providing low leakage current capacitors and optimizing step coverage for high aspect ratio features.
2. Background of the Related Art
Dynamic random-access memory (DRAM) integrated circuits are commonly used for storing data in a digital computer. Currently available DRAMs may contain over 16 million cells fabricated on a single crystal silicon chip, wherein each memory cell generally comprises a single transistor connected to a miniature capacitor. In operation, each capacitor may be individually charged or discharged in order to store one bit of information. A DRAM is dynamic in the sense that charged memory cells must be refreshed or recharged periodically to maintain data integrity. Otherwise, charged memory cells may discharge through leakage to a level where they no longer appear to be set to a charged state.
To facilitate construction of 64 MB, 256 MB, 1 GB and higher density DRAMs with correspondingly smaller-sized memory cells, capacitor structures and materials that can store the charge in smaller chip space are needed. High dielectric constant (HDC) materials (defined herein as having a dielectric constant greater than about 50) have been used successfully in such capacitor structures in many microelectronic applications, such as DRAM and infrared detectors. It is desirable that such materials used for DRAMs and other microelectronic applications be formable over an electrode and underlying structure without significant harm to the electrode and the underlying structure. It is also desirable to have the resulting device to have dielectric materials that exhibit low leakage current (i.e., the electrical current flowing from one electrode of the capacitor to the other electrode of the capacitor during operation of the capacitor) and consistent dielectric properties throughout the lifetime of the device and also possess high dielectric constants at frequencies of hundreds of MHz up to several GHz. Examples of HDC materials used in capacitor structures in microelectronic devices include lead lanthanium titanate (PLT), barium titanate, strontium titanate and barium strontium titanate (BST). Other materials that may be used in capacitor structures in non-volatile memory cells include ferroelectric materials, such as lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT).
In a highly integrated device such as a 1 GB, the isolation widths between neighboring electrodes are approaching 0.3 xcexcm or smaller, and the thickness of the electrodes are becoming larger than the isolation width. For example, FIG. 1 shows a sectional view of a prior art microelectronic device 8 having two capacitor structures 12a and 12b having a small isolation width 24 ( less than 0.31 xcexcm). The microelectronic device 8 includes an active device layer 10 (in which active devices such as transistors are formed with appropriate wirings and terminals) and two capacitor structures 12a and 12b, including two platinum bottom electrodes 14a and 14b, an insulator 16, an upper platinum electrode 18. Conductive plugs 20a and 20b connect the bottom electrodes 14a and 14b with devices in the active device layer 10 through an insulating layer 22. A coupling capacitance between the two neighboring electrodes 14a and 14b results because the isolation width 24 between the neighboring electrodes 14a and 14b is small ( less than 0.3 xcexcm) and the dielectric material between the electrodes 14a and 14b does not have a sufficiently high dielectric constant to prevent the coupling capacitance.
The coupling capacitance between neighboring electrodes 14a and 14b can cause instabilities in the circuit operation. This coupling capacitance causes instabilities in the circuit operation because the capacitance of each of the capacitor structures 12a and 12b is distorted by the coupling capacitance. For example, when the electrodes of the capacitors are charged during operation of the device, the coupling capacitance between the neighboring bottom electrodes 14a and 14b may become higher than the capacitance between the upper electrode 18 and each of the bottom electrodes 14a and 14b because of the small isolation width 24 (less than 0.3 xcexcm) and the high aspect ratio (i.e., the height 26 of the bottom electrodes 14a and 14b is greater than the width 24 between the bottom electrodes 14a and 14b).
A further problem involving lateral leakage current occurs as a result of a decrease in the distance or isolation width 24 between the bottom electrodes 14a and 14b. The lateral leakage current is current that flows between bottom electrodes 14a and 14b when the capacitor structures 12a and 12b are charged up during operation. When the distance or isolation width 24 between neighboring electrodes 14a and 14b is greater than 1 xcexcm, as in low level integration, the lateral leakage current is insignificant and not problematic because a sufficient amount of dielectric material separates the neighboring electrodes 14a and 14b. However, as the isolation width 24 approaches 0.3 xcexcm and smaller, the lateral leakage current increases significantly to a problematic level that may cause breakdown of the capacitors. The lateral leakage current results because it is difficult to nucleate high k dielectric materials with adequate dielectric characteristics into the smaller isolation width between the neighboring electrodes 14a and 14b. In light of the above, proper nucleation of the high k dielectric material in these high aspect ratio isolation widths is needed to reduce the lateral current leakage and the coupling capacitance between the neighboring electrodes.
HDC materials, such as BST, have been deposited in bulk form and have stable properties. However, this is not true for thin film (200-300xc3x85) properties of BST. For example, dielectric constant and leakage current are severely degraded as compared to bulk BST, that is, the dielectric constant reduces to about 10-20% of the dielectric constant of bulk BST and the leakage current increases to 5 to 10 times higher than the leakage current of bulk BST. Current methods of depositing BST films are unable to achieve the high dielectric constant and low leakage current required in applications in sub-micron devices that require BST film thickness less than 300 xc3x85 thick.
Therefore, there remains a need for an apparatus and a method for manufacturing capacitors having high quality HDC materials and low leakage currents between neighboring electrodes for use in high density DRAMs. There is also a need for a method for nucleating thin, high quality HDC dielectric films for use in high density semiconductor devices. There also remains a need for an apparatus and a method for manufacturing capacitors having high quality HDC materials and low leakage currents within a high aspect ratio aperture, particularly within features that are less than 0.31 xcexcm wide.
The present invention provides a multi-layer semiconductor memory device comprising: a bottom electrode comprising a bottom layer, an upper interface layer and an intermediate tuning layer between the bottom layer and the upper interface layer; a top electrode; and a high dielectric constant layer disposed between the bottom electrode and the top electrode. Preferably, the bottom layer of the bottom electrode comprises a barrier material such as titanium or a combination of titanium and titanium nitride, and the upper layer of the bottom electrode comprises an interface material having high work function and oxidation resistance such as platinum, ruthenium, iridium, rhodium, platinum combined with rhodium, platinum combined with iridium, platinum combined with ruthenium and combinations thereof. Preferably, the tuning layer comprises a material such as ruthenium oxide (RuO2), ruthenium combined with ruthenium oxide (Ru/RuO2), iridium oxide (IrO2), iridium combined with iridium oxide (Ir/IrO2), titanium aluminum nitride (TiAlN) and combinations thereof. The top electrode preferably comprises the same material as the upper layer of the bottom electrode, and the preferred HDC material includes barium strontium titanate (BST), lead zirconate titanate (PZT), lead lanthanium titanate (PLT), barium titanate, strontium titanate and strontium bismuth titanate (SBT).
The present invention further provides a method for manufacturing capacitors for high density DRAMs having high quality HDC dielectrics and low leakage currents in a high aspect ratio device feature comprising: depositing a material by PVD and redepositing and distributing the same material using a high density plasma (HDP) PVD or a Pulsed DC Densifying Plasma.
Another aspect of the invention provides an electrode-dielectric interface that nucleates high quality HDC films. The present invention provides an interface layer that is tuned by an underlayer for optimal nucleation of the HDC film. Preferably, the tuning layer comprises a material such as ruthenium oxide (RuO2), ruthenium combined with ruthenium oxide (Ru/RuO2), iridium oxide (IrO2), iridium combined with iridium oxide (Ir/IrO2), titanium aluminum nitride (TiAlN) and combinations thereof The interface layer preferably comprises an interface material having high work function and oxidation resistance such as platinum, ruthenium, iridium, rhodium, platinum combined with rhodium, platinum combined with iridium, platinum combined with ruthenium and combinations thereof.